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NAME

CPU_ELAN - AMD Elan 520 CPU support

CONTENTS

Synopsis
Description
See Also
History
Authors

SYNOPSIS


.Cd "options CPU_ELAN"
.Cd "options CPU_ELAN_PPS"
.Cd "options CPU_ELAN_XTAL"
machdep.elan_gpio_config
machdep.elan_freq

.Cd "options CPU_SOEKRIS"

DESCRIPTION

The
.Cd "options CPU_ELAN" enables support for the AMD Elan 520 CPU.

A device /dev/elan-mmcr exports the MMCR register bank to userland using mmap(2).

The i8254 timer will be adjusted to the slightly unorthodox frequency 1189161 Hz (32768 * 45 * 25 / 31) employed by the Elan.

A timecounter named "ELAN" is implemented using the general purpose timer 2, but it will not be usable unless HZ is configured at 150 or higher. This timecounter is much better than the "i8254" timecounter and should be used at all times.

The machdep.elan_gpio_config sysctl(8) variable enables configuration of the GPIO pins of the CPU. The string must be exactly 32 characters long. A ‘-’ means the GPIO is unavailable. A ‘l’ (lower-case ell) configures a led(4) device (active low). A ‘L’ configures a led(4) device (active high). A ‘.’ means no configuration for this GPIO. These led(4) devices will be named /dev/led/gpio%d. For meaning of ‘P’, ‘e’ and ‘E’, see under
.Cd "options CPU_ELAN_PPS" .

The
.Cd "options CPU_ELAN_XTAL" and the machdep.elan_freq sysctl(8) variable can be used to set the CPU clock crystal frequency in Hz. The default is 33333333 Hz.

The
.Cd "options CPU_ELAN_PPS" enables precision timestamping using the RFC2783 PPS-API via the /dev/elan-mmcr device. The resolution will be approximately 125 nsec and the precision ± 125 nsec. (For 125 nsec read ""4 / CPU clock crystal frequency".")

The input signal must be connected to the TMR1IN pin and a GPIO pin. The GPIO pin must be configured with a ‘P’ in machdep.elan_gpio_config.

In addition, one GPIO pin can be configured with either ‘e’ (active low) or ‘E’ (active high) to become a "echo" output of the input signal. Please notice that this signal is not suitable for calibration.

If the
.Cd "options CPU_SOEKRIS" is given, the support will additionally be tailored to the Soekris Engineering 45xx series of embedded computers. The "error" led will be configured (as /dev/led/error) and the GPIO pins which are not available will be disabled.

SEE ALSO

led(4), sysctl(8)

HISTORY

AUTHORS


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