Memory Barriers
Memory barriers are used to guarantee the order of data accesses in two ways. First, they specify hints to the compiler to not re-order or optimize the operations. Second, on architectures that do not guarantee ordered data accesses, special instructions or special variants of instructions are used to indicate to the processor that data accesses need to occur in a certain order. As a result, most of the atomic operations have three variants in order to include optional memory barriers. The first form just performs the operation without any explicit barriers. The second form uses a read memory barrier, and the third variant uses a write memory barrier. The second variant of each operation includes a read memory barrier. This barrier ensures that the effects of this operation are completed before the effects of any later data accesses. As a result, the operation is said to have acquire semantics as it acquires a pseudo-lock requiring further operations to wait until it has completed. To denote this, the suffix "_acq" is inserted into the function name immediately prior to the "_<type>" suffix. For example, to subtract two integers ensuring that any later writes will happen after the subtraction is performed, use atomic_subtract_acq_int.
The third variant of each operation includes a write memory barrier. This ensures that all effects of all previous data accesses are completed before this operation takes place. As a result, the operation is said to have release semantics as it releases any pending data accesses to be completed before its operation is performed. To denote this, the suffix "_rel" is inserted into the function name immediately prior to the "_<type>" suffix. For example, to add two long integers ensuring that all previous writes will happen first, use atomic_add_rel_long.
A practical example of using memory barriers is to ensure that data accesses that are protected by a lock are all performed while the lock is held. To achieve this, one would use a read barrier when acquiring the lock to guarantee that the lock is held before any protected operations are performed. Finally, one would use a write barrier when releasing the lock to ensure that all of the protected operations are completed before the lock is released.
Multiple Processors
The current set of atomic operations do not necessarily guarantee atomicity across multiple processors. To guarantee atomicity across processors, not only does the individual operation need to be atomic on the processor performing the operation, but the result of the operation needs to be pushed out to stable storage and the caches of all other processors on the system need to invalidate any cache lines that include the affected memory region. On the i386 architecture, the cache coherency model requires that the hardware perform this task, thus the atomic operations are atomic across multiple processors. On the ia64 architecture, coherency is only guaranteed for pages that are configured to using a caching policy of either uncached or write back.
Semantics
This section describes the semantics of each operation using a C like notation.
