PMC (3) | C library functions | Unix Manual Pages

PMC (3) | C library functions | Unix Manual Pages | :man▋

PMCs are allocated using pmc_allocate, released using pmc_release and read using pmc_read. Allocated PMCs may be started or stopped at any time using pmc_start and pmc_stop respectively. An allocated PMC may be of "global" scope, meaning that the PMC measures system-wide events, or "process-private" scope, meaning that the PMC only counts hardware events when the allocating process (or, optionally, its children) are active.

PMCs may further be in ""counting mode"", or in ""sampling mode"". Sampling mode PMCs deliver an interrupt to the CPU after a configured number of hardware events have been seen. A process-private sampling mode PMC will cause its owner process to get periodic SIGPROF interrupts, while a global sampling mode PMC is used to do system-wide statistical sampling (see hwpmc(4)). The sampling rate desired of a sampling-mode PMC is set using pmc_set. Counting mode PMCs do not interrupt the CPU; their values can be read using pmc_read.

System-wide statistical sampling is configured by allocating at least one sampling mode PMC with global scope, and when a log file is configured using pmc_configure_logfile. The hwpmc(4) driver manages system-wide statistical sampling; for more information please see hwpmc(4).

Application Programming Interface

The function pmc_init initializes the pmc(3) library. This function must be called first, before any of the other functions in the library.

The function pmc_allocate allocates a counter that counts the events named by eventspecifier, and writes the allocated counter ID to *pmcid. Argument eventspecifier comprises an PMC event name followed by an optional comma separated list of keywords and qualifiers. The allowed syntax for eventspecifier is processor architecture specific and is listed in section "EVENT SPECIFIERS" below. The desired PMC mode is specified by mode, and any mode specific modifiers are specified using flags. The cpu argument is the value PMC_CPU_ANY, or names the CPU the allocation is to be on. Requesting a specific CPU only makes sense for global PMCs; process-private PMC allocations should always specify PMC_CPU_ANY.

By default, a PMC configured in process-virtual counting mode is set up to profile its owner process. The function pmc_attach may be used to attach the PMC to a different process. It needs to be called before the counter is first started with pmc_start. The function pmc_detach may be used to detach a PMC from a process it was attached to using a prior call to pmc_attach.

The function pmc_release releases a PMC previously allocated with pmc_allocate. This function call implicitly detaches the PMC from all its target processes.

An allocated PMC may be started and stopped using pmc_start and pmc_stop respectively.

The current value of a PMC may be read with pmc_read and written using pmc_write, provided the underlying hardware supports these operations on the allocated PMC. The read and write operation may be combined using pmc_rw.

The function pmc_capabilities sets argument caps to a bitmask of capabilities supported by the PMC denoted by argument pmc. The function pmc_width sets argument width to the width of the PMC denoted by argument pmc.

The pmc_configure_logfile function causes the hwpmc(4) driver to log performance data to file corresponding to the process’ file handle fd. If argument fd is -1, then any previously configured logging is reset and all data queued to be written are discarded.

The pmc_flush_logfile function will send all data queued inside the hwpmc(4) driver to the configured log file before returning. The pmc_writelog function will append a log entry containing the argument userdata to the log file.

The function pmc_set configures a sampling PMC pmc to interrupt every value events. For counting PMCs, pmc_set sets the initial value of the PMC to value.

The function pmc_get_driver_statistics copies a snapshot of the usage statistics maintained by hwpmc(4) into the memory area pointed to by argument gms.

Signal Handling Requirements

Applications using PMCs are required to handle the following signals:

`SIGBUS`
	When the hwpmc(4) module is unloaded using kldunload(8), processes that have PMCs allocated to them will be sent a `SIGBUS` signal.
`SIGIO`	The hwpmc(4) driver will send a PMC owning process a `SIGIO` signal if: If any process-mode PMC allocated by it loses all its target processes. If the driver encounters an error when writing log data to a configured log file. This error may be retrieved by a subsequent call to `pmc_flush_logfile`.

Convenience Functions

The function pmc_ncpu returns the number of CPUs present in the system.

The function pmc_npmc returns the number of PMCs supported on CPU cpu. The function pmc_cpuinfo sets argument cpu_info to point to a structure with information about the system’s CPUs. Function pmc_pmcinfo returns information about the current state of CPU cpu ’s PMCs. This function sets argument *pmc_info to point to a memory area allocated with calloc(3). The caller is expected to free the area when done.

The functions pmc_name_of_capability, pmc_name_of_class, pmc_name_of_cputype, pmc_name_of_disposition, pmc_name_of_event, pmc_name_of_mode and pmc_name_of_state are useful for code wanting to print error messages. They return
.Vt "const char *" pointers to human-readable representations of their arguments. These return values should not be freed using free(3).

The function pmc_event_names_of_class returns a list of event names supported by a given PMC class cl. On successful return, an array of
.Vt "const char *" pointers to the names of valid events supported by class cl is allocated by the library using malloc(3), and a pointer to this array is returned in the location pointed to by eventnames. The number of pointers allocated is returned in the location pointed to by nevents.

Administration

Individual PMCs may be enabled or disabled on a given CPU using pmc_enable and pmc_disable respectively. For these functions, cpu is the CPU number, and pmc is the index of the PMC to be operated on. Only the super-user is allowed to enable and disable PMCs.

x86 Architecture Specific API

The pmc_get_msr function returns the processor model specific register number associated with pmc. Applications may use the x86 RDPMC instruction to directly read the contents of the PMC.

EVENT SPECIFIERS

Event specifiers are strings comprising of an event name, followed by optional parameters modifying the semantics of the hardware event being probed. Event names are PMC architecture dependent, but the hwpmc(4) library defines machine independent aliases for commonly used events.

Event Name Aliases

Event name aliases are CPU architecture independent names for commonly used events. The following aliases are known to this version of the pmc(3) library:

branches
	Measure the number of branches retired.
branch-mispredicts
	Measure the number of retired branches that were mispredicted.
cycles
	Measure processor cycles. This event is implemented using the processor’s Time Stamp Counter register.
dc-misses
	Measure the number of data cache misses.
ic-misses
	Measure the number of instruction cache misses.
instructions
	Measure the number of instructions retired.
interrupts
	Measure the number of interrupts seen.

Time Stamp Counter (TSC)

The timestamp counter is a monotonically non-decreasing counter that counts processor cycles.

In the i386 architecture, this counter may be selected by requesting an event with event specifier "tsc". The "tsc" event does not support any further qualifiers. It can only be allocated in system-wide counting mode, and is a read-only counter. Multiple processes are allowed to allocate the TSC. Once allocated, it may be read using the pmc_read function, or by using the RDTSC instruction.

AMD (K7) PMCs

These PMCs are present in the "AMD Athlon" series of CPUs and are documented in:
.Rs
.Re

Event specifiers for AMD K7 PMCs can have the following optional qualifiers:

count= value
	Configure the counter to increment only if the number of configured events measured in a cycle is greater than or equal to value.
edge	Configure the counter to only count negated-to-asserted transitions of the conditions expressed by the other qualifiers. In other words, the counter will increment only once whenever a given condition becomes true, irrespective of the number of clocks during which the condition remains true.
inv	Invert the sense of comparision when the "count" qualifier is present, making the counter to increment when the number of events per cycle is less than the value specified by the "count" qualifier.
os	Configure the PMC to count events happening at privilege level 0.
unitmask= mask
	This qualifier is used to further qualify a select few events, "k7-dc-refills-from-l2", "k7-dc-refills-from-system" and "k7-dc-writebacks". Here mask is a string of the following characters optionally separated by ‘`+`’ characters:
m	Count operations for lines in the "Modified" state.
o	Count operations for lines in the "Owner" state.
e	Count operations for lines in the "Exclusive" state.
s	Count operations for lines in the "Shared" state.
i	Count operations for lines in the "Invalid" state.

If no "unitmask" qualifier is specified, the default is to count events for caches lines in any of the above states.

usr	Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the "os" or "usr" qualifiers were specified, the default is to enable both.

The event specifiers supported on AMD K7 PMCs are:

k7-dc-accesses
	Count data cache accesses.
k7-dc-misses
	Count data cache misses.
k7-dc-refills-from-l2 [,unitmask= mask]
	Count data cache refills from L2 cache. This event may be further qualified using the "unitmask" qualifier.
k7-dc-refills-from-system [,unitmask= mask]
	Count data cache refills from system memory. This event may be further qualified using the "unitmask" qualifier.
k7-dc-writebacks [,unitmask= mask]
	Count data cache writebacks. This event may be further qualified using the "unitmask" qualifier.
k7-l1-dtlb-miss-and-l2-dtlb-hits
	Count L1 DTLB misses and L2 DTLB hits.
k7-l1-and-l2-dtlb-misses
	Count L1 and L2 DTLB misses.
k7-misaligned-references
	Count misaligned data references.
k7-ic-fetches
	Count instruction cache fetches.
k7-ic-misses
	Count instruction cache misses.
k7-l1-itlb-misses
	Count L1 ITLB misses that are L2 ITLB hits.
k7-l1-l2-itlb-misses
	Count L1 (and L2) ITLB misses.
k7-retired-instructions
	Count all retired instructions.
k7-retired-ops
	Count retired ops.
k7-retired-branches
	Count all retired branches (conditional, unconditional, exceptions and interrupts).
k7-retired-branches-mispredicted
	Count all misprediced retired branches.
k7-retired-taken-branches
	Count retired taken branches.
k7-retired-taken-branches-mispredicted
	Count mispredicted taken branches that were retired.
k7-retired-far-control-transfers
	Count retired far control transfers.
k7-retired-resync-branches
	Count retired resync branches (non control transfer branches).
k7-interrupts-masked-cycles
	Count the number of cycles when the processor’s IF flag was zero.
k7-interrupts-masked-while-pending-cycles
	Count the number of cycles interrupts were masked while pending due to the processor’s IF flag being zero.
k7-hardware-interrupts
	Count the number of taken hardware interrupts.

AMD (K8) PMCs

These PMCs are present in the "AMD Athlon64" and "AMD Opteron" series of CPUs. They are documented in:
.Rs
.Re

Event specifiers for AMD K8 PMCs can have the following optional qualifiers:

count= value
	Configure the counter to increment only if the number of configured events measured in a cycle is greater than or equal to value.
edge	Configure the counter to only count negated-to-asserted transitions of the conditions expressed by the other fields. In other words, the counter will increment only once whenever a given condition becomes true, irrespective of the number of clocks during which the condition remains true.
inv	Invert the sense of comparision when the "count" qualifier is present, making the counter to increment when the number of events per cycle is less than the value specified by the "count" qualifier.
mask= qualifier
	Many event specifiers for AMD K8 PMCs need to be additionally qualified using a mask qualifier. These additional qualifiers are event-specific and are documented along with their associated event specifiers below.
os	Configure the PMC to count events happening at privilege level 0.
usr	Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the "os" or "usr" qualifiers were specified, the default is to enable both.

The event specifiers supported on AMD K8 PMCs are:

k8-bu-cpu-clk-unhalted
	Count the number of clock cycles when the CPU is not in the HLT or STPCLK states.
k8-bu-fill-request-l2-miss [,mask= qualifier]
	Count fill requests that missed in the L2 cache. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
dc-fill
	Count data cache fill requests.
ic-fill
	Count instruction cache fill requests.
tlb-reload
	Count TLB reloads.

The default is to count all types of requests.

k8-bu-internal-l2-request [,mask= qualifier]
	Count internally generated requests to the L2 cache. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
cancelled
	Count cancelled requests.
dc-fill
	Count data cache fill requests.
ic-fill
	Count instruction cache fill requests.
tag-snoop
	Count tag snoop requests.
tlb-reload
	Count TLB reloads.

The default is to count all types of requests.

k8-dc-access
	Count data cache accesses including microcode scratchpad accesses.
k8-dc-copyback [,mask= qualifier]
	Count data cache copyback operations. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
exclusive
	Count operations for lines in the "exclusive" state.
invalid
	Count operations for lines in the "invalid" state.
modified
	Count operations for lines in the "modified" state.
owner	Count operations for lines in the "owner" state.
shared
	Count operations for lines in the "shared" state.

The default is to count operations for lines in all the above states.

k8-dc-dcache-accesses-by-locks [,mask= qualifier]
	Count data cache accesses by lock instructions. This event is only available on processors of revision C or later vintage. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
accesses
	Count data cache accesses by lock instructions.
misses
	Count data cache misses by lock instructions.

The default is to count all accesses.

k8-dc-dispatched-prefetch-instructions [,mask= qualifier]
	Count the number of dispatched prefetch instructions. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
load	Count load operations.
nta	Count non-temporal operations.
store	Count store operations.

The default is to count all operations.

k8-dc-l1-dtlb-miss-and-l2-dtlb-hit
	Count L1 DTLB misses that are L2 DTLB hits.
k8-dc-l1-dtlb-miss-and-l2-dtlb-miss
	Count L1 DTLB misses that are also misses in the L2 DTLB.
k8-dc-microarchitectural-early-cancel-of-an-access
	Count microarchitectural early cancels of data cache accesses.
k8-dc-microarchitectural-late-cancel-of-an-access
	Count microarchitectural late cancels of data cache accesses.
k8-dc-misaligned-data-reference
	Count misaligned data references.
k8-dc-miss
	Count data cache misses.
k8-dc-one-bit-ecc-error [,mask= qualifier]
	Count one bit ECC errors found by the scrubber. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
scrubber
	Count scrubber detected errors.
piggyback
	Count piggyback scrubber errors.

The default is to count both kinds of errors.

k8-dc-refill-from-l2 [,mask= qualifier]
	Count data cache refills from L2 cache. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
exclusive
	Count operations for lines in the "exclusive" state.
invalid
	Count operations for lines in the "invalid" state.
modified
	Count operations for lines in the "modified" state.
owner	Count operations for lines in the "owner" state.
shared
	Count operations for lines in the "shared" state.

The default is to count operations for lines in all the above states.

k8-dc-refill-from-system [,mask= qualifier]
	Count data cache refills from system memory. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
exclusive
	Count operations for lines in the "exclusive" state.
invalid
	Count operations for lines in the "invalid" state.
modified
	Count operations for lines in the "modified" state.
owner	Count operations for lines in the "owner" state.
shared
	Count operations for lines in the "shared" state.

The default is to count operations for lines in all the above states.

k8-fp-dispatched-fpu-ops [,mask= qualifier]
	Count the number of dispatched FPU ops. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
add-pipe-excluding-junk-ops
	Count add pipe ops excluding junk ops.
add-pipe-junk-ops
	Count junk ops in the add pipe.
multiply-pipe-excluding-junk-ops
	Count multiply pipe ops excluding junk ops.
multiply-pipe-junk-ops
	Count junk ops in the multiply pipe.
store-pipe-excluding-junk-ops
	Count store pipe ops excluding junk ops
store-pipe-junk-ops
	Count junk ops in the store pipe.

The default is to count all types of ops.

k8-fp-cycles-with-no-fpu-ops-retired
	Count cycles when no FPU ops were retired. This event is supported in revision B and later CPUs.
k8-fp-dispatched-fpu-fast-flag-ops
	Count dispatched FPU ops that use the fast flag interface. This event is supported in revision B and later CPUs.
k8-fr-decoder-empty
	Count cycles when there was nothing to dispatch (i.e., the decoder was empty).
k8-fr-dispatch-stalls
	Count all dispatch stalls.
k8-fr-dispatch-stall-for-segment-load
	Count dispatch stalls for segment loads.
k8-fr-dispatch-stall-for-serialization
	Count dispatch stalls for serialization.
k8-fr-dispatch-stall-from-branch-abort-to-retire
	Count dispatch stalls from branch abort to retiral.
k8-fr-dispatch-stall-when-fpu-is-full
	Count dispatch stalls when the FPU is full.
k8-fr-dispatch-stall-when-ls-is-full
	Count dispatch stalls when the load/store unit is full.
k8-fr-dispatch-stall-when-reorder-buffer-is-full
	Count dispatch stalls when the reorder buffer is full.
k8-fr-dispatch-stall-when-reservation-stations-are-full
	Count dispatch stalls when reservation stations are full.
k8-fr-dispatch-stall-when-waiting-for-all-to-be-quiet
	Count dispatch stalls when waiting for all to be quiet.
k8-fr-dispatch-stall-when-waiting-far-xfer-or-resync-branch-pending
	Count dispatch stalls when a far control transfer or a resync branch is pending.
k8-fr-fpu-exceptions [,mask= qualifier]
	Count FPU exceptions. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
sse-and-x87-microtraps
	Count SSE and x87 microtraps.
sse-reclass-microfaults
	Count SSE reclass microfaults
sse-retype-microfaults
	Count SSE retype microfaults
x87-reclass-microfaults
	Count x87 reclass microfaults.

The default is to count all types of exceptions.

k8-fr-interrupts-masked-cycles
	Count cycles when interrupts were masked (by CPU RFLAGS field IF was zero).
k8-fr-interrupts-masked-while-pending-cycles
	Count cycles while interrupts were masked while pending (i.e., cycles when INTR was asserted while CPU RFLAGS field IF was zero).
k8-fr-number-of-breakpoints-for-dr0
	Count the number of breakpoints for DR0.
k8-fr-number-of-breakpoints-for-dr1
	Count the number of breakpoints for DR1.
k8-fr-number-of-breakpoints-for-dr2
	Count the number of breakpoints for DR2.
k8-fr-number-of-breakpoints-for-dr3
	Count the number of breakpoints for DR3.
k8-fr-retired-branches
	Count retired branches including exceptions and interrupts.
k8-fr-retired-branches-mispredicted
	Count mispredicted retired branches.
k8-fr-retired-far-control-transfers
	Count retired far control transfers (which are always mispredicted).
k8-fr-retired-fastpath-double-op-instructions [,mask= qualifier]
	Count retired fastpath double op instructions. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
low-op-pos-0
	Count instructions with the low op in position 0.
low-op-pos-1
	Count instructions with the low op in position 1.
low-op-pos-2
	Count instructions with the low op in position 2.

The default is to count all types of instructions.

k8-fr-retired-fpu-instructions [,mask= qualifier]
	Count retired FPU instructions. This event is supported in revision B and later CPUs. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
mmx-3dnow
	Count MMX and 3DNow! instructions.
packed-sse-sse2
	Count packed SSE and SSE2 instructions.
scalar-sse-sse2
	Count scalar SSE and SSE2 instructions
x87	Count x87 instructions.

The default is to count all types of instructions.

k8-fr-retired-near-returns
	Count retired near returns.
k8-fr-retired-near-returns-mispredicted
	Count mispredicted near returns.
k8-fr-retired-resyncs
	Count retired resyncs (non-control transfer branches).
k8-fr-retired-taken-hardware-interrupts
	Count retired taken hardware interrupts.
k8-fr-retired-taken-branches
	Count retired taken branches.
k8-fr-retired-taken-branches-mispredicted
	Count retired taken branches that were mispredicted.
k8-fr-retired-taken-branches-mispredicted-by-addr-miscompare
	Count retired taken branches that were mispredicted only due to an address miscompare.
k8-fr-retired-uops
	Count retired uops.
k8-fr-retired-x86-instructions
	Count retired x86 instructions including exceptions and interrupts.
k8-ic-fetch
	Count instruction cache fetches.
k8-ic-instruction-fetch-stall
	Count cycles in stalls due to instruction fetch.
k8-ic-l1-itlb-miss-and-l2-itlb-hit
	Count L1 ITLB misses that are L2 ITLB hits.
k8-ic-l1-itlb-miss-and-l2-itlb-miss
	Count ITLB misses that miss in both L1 and L2 ITLBs.
k8-ic-microarchitectural-resync-by-snoop
	Count microarchitectural resyncs caused by snoops.
k8-ic-miss
	Count instruction cache misses.
k8-ic-refill-from-l2
	Count instruction cache refills from L2 cache.
k8-ic-refill-from-system
	Count instruction cache refills from system memory.
k8-ic-return-stack-hits
	Count hits to the return stack.
k8-ic-return-stack-overflow
	Count overflows of the return stack.
k8-ls-buffer2-full
	Count load/store buffer2 full events.
k8-ls-locked-operation [,mask= qualifier]
	Count locked operations. For revision C and later CPUs, the following qualifiers are supported:
cycles-in-request
	Count the number of cycles in the lock request/grant stage.
cycles-to-complete
	Count the number of cycles a lock takes to complete once it is non-speculative and is the older load/store operation.
locked-instructions
	Count the number of lock instructions executed.

The default is to count the number of lock instructions executed.

k8-ls-microarchitectural-late-cancel
	Count microarchitectural late cancels of operations in the load/store unit.
k8-ls-microarchitectural-resync-by-self-modifying-code
	Count microarchitectural resyncs caused by self-modifying code.
k8-ls-microarchitectural-resync-by-snoop
	Count microarchitectural resyncs caused by snoops.
k8-ls-retired-cflush-instructions
	Count retired CFLUSH instructions.
k8-ls-retired-cpuid-instructions
	Count retired CPUID instructions.
k8-ls-segment-register-load [,mask= qualifier]
	Count segment register loads. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
cs	Count CS register loads.
ds	Count DS register loads.
es	Count ES register loads.
fs	Count FS register loads.
gs	Count GS register loads.
ss	Count SS register loads.

The default is to count all types of loads.

k8-nb-memory-controller-bypass-saturation [,mask= qualifier]
	Count memory controller bypass counter saturation events. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
dram-controller-interface-bypass
	Count DRAM controller interface bypass.
dram-controller-queue-bypass
	Count DRAM controller queue bypass.
memory-controller-hi-pri-bypass
	Count memory controller high priority bypasses.
memory-controller-lo-pri-bypass
	Count memory controller low priority bypasses.

k8-nb-memory-controller-dram-slots-missed
	Count memory controller DRAM command slots missed (in MemClks).
k8-nb-memory-controller-page-access-event [,mask= qualifier]
	Count memory controller page access events. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
page-conflict
	Count page conflicts.
page-hit
	Count page hits.
page-miss
	Count page misses.

The default is to count all types of events.

k8-nb-memory-controller-page-table-overflow
	Count memory control page table overflow events.
k8-nb-probe-result [,mask= qualifier]
	Count probe events. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
probe-hit
	Count all probe hits.
probe-hit-dirty-no-memory-cancel
	Count probe hits without memory cancels.
probe-hit-dirty-with-memory-cancel
	Count probe hits with memory cancels.
probe-miss
	Count probe misses.

k8-nb-sized-commands [,mask= qualifier]
	Count sized commands issued. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
nonpostwrszbyte nonpostwrszdword postwrszbyte postwrszdword rdszbyte rdszdword rdmodwr

The default is to count all types of commands.

k8-nb-memory-controller-turnaround [,mask= qualifier]
	Count memory control turnaround events. This event may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
dimm-turnaround
	Count DIMM turnarounds.
read-to-write-turnaround
	Count read to write turnarounds.
write-to-read-turnaround
	Count write to read turnarounds.

The default is to count all types of events.

k8-nb-ht-bus0-bandwidth [,mask= qualifier] k8-nb-ht-bus1-bandwidth [,mask= qualifier] k8-nb-ht-bus2-bandwidth [,mask= qualifier]
	Count events on the HyperTransport(tm) buses. These events may be further qualified using qualifier, which is a ‘`+`’ separated set of the following keywords:
buffer-release
	Count buffer release messages sent.
command
	Count command messages sent.
data	Count data messages sent.
nop	Count nop messages sent.

The default is to count all types of messages.

Intel P6 PMCS

Intel P6 PMCs are present in Intel "Pentium Pro", "Pentium II", Celeron, "Pentium III" and "Pentium M" processors.

These CPUs have two counters. Some events may only be used on specific counters and some events are defined only on specific processor models.

These PMCs are documented in
.Rs "Volume 3: System Programming Guide"
.Re

Some of these events are affected by processor errata described in
.Rs
.Re

Event specifiers for Intel P6 PMCs can have the following common qualifiers:

cmask= value
	Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to value.
edge	Configure the PMC to count the number of deasserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.
inv	Invert the sense of comparision when the "cmask" qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the "cmask" qualifier.
os	Configure the PMC to count events happening at processor privilege level 0.
umask= value
	This qualifier is used to further qualify the event selected (see below).
usr	Configure the PMC to count events occurring at privilege levels 1, 2 or 3.

If neither of the "os" or "usr" qualifiers are specified, the default is to enable both.

The event specifiers supported by Intel P6 PMCs are:

p6-baclears
	Count the number of times a static branch prediction was made by the branch decoder because the BTB did not have a prediction.
p6-br-bac-missp-exec
	("Pentium M") Count the number of branch instructions executed that where mispredicted at the Front End (BAC).
p6-br-bogus
	Count the number of bogus branches.
p6-br-call-exec
	("Pentium M") Count the number of call instructions executed.
p6-br-call-missp-exec
	("Pentium M") Count the number of call instructions executed that were mispredicted.
p6-br-cnd-exec
	("Pentium M") Count the number of conditional branch instructions executed.
p6-br-cnd-missp-exec
	("Pentium M") Count the number of conditional branch instructions executed that were mispredicted.
p6-br-ind-call-exec
	("Pentium M") Count the number of indirect call instructions executed.
p6-br-ind-exec
	("Pentium M") Count the number of indirect branch instructions executed.
p6-br-ind-missp-exec
	("Pentium M") Count the number of indirect branch instructions executed that were mispredicted.
p6-br-inst-decoded
	Count the number of branch instructions decoded.
p6-br-inst-exec
	("Pentium M") Count the number of branch instructions executed but necessarily retired.
p6-br-inst-retired
	Count the number of branch instructions retired.
p6-br-miss-pred-retired
	Count the number of mispredicted branch instructions retired.
p6-br-miss-pred-taken-ret
	Count the number of taken mispredicted branches retired.
p6-br-missp-exec
	("Pentium M") Count the number of branch instructions executed that were mispredicted at execution.
p6-br-ret-bac-missp-exec
	("Pentium M") Count the number of return instructions executed that were mispredicted at the Front End (BAC).
p6-br-ret-exec
	("Pentium M") Count the number of return instructions executed.
p6-br-ret-missp-exec
	("Pentium M") Count the number of return instructions executed that were mispredicted at execution.
p6-br-taken-retired
	Count the number of taken branches retired.
p6-btb-misses
	Count the number of branches for which the BTB did not produce a prediction.
p6-bus-bnr-drv
	Count the number of bus clock cycles during which this processor is driving the BNR# pin.
p6-bus-data-rcv
	Count the number of bus clock cycles during which this processor is receiving data.
p6-bus-drdy-clocks [,umask= qualifier]
	Count the number of clocks during which DRDY# is asserted. An additional qualifier may be specified, and comprises one of the following keywords:
any	Count transactions generated by any agent on the bus.
self	Count transactions generated by this processor.